Decimal multiplication using compressor based-BCD to binary converter

Decimal multiplication using compressor based-BCD to binary converter

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The objective of this work is to implement a scalable decimal to binary converter from 8 to 64 bits (i.e 2-digit to 16-digit) using parallel architecture.The proposed converters, along with binary coded decimal (BCD) adder and binary to BCD converters, are used in parallel implementation of Urdhva Triyakbhyam (UT)-based 32-bit BCD multiplier.To increase the performance, compressor circuits were used in converters and multiplier.

The designed hardware circuits were verified viqua-f4 by behavioural and post layout simulations.The implementation feline 1-hcpch vaccine was carried out using Virtex-6 Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) with 90-nm technology library platforms.The results on FPGA shows that compressor based converters and multipliers produced less amount of propagation delay with a slight increase of hardware resources.In case of ASIC implementation, a compressor based converter delay is equivalent to conventional converter with a slight increase of gate count.

However, the reduction of delay is evident in case of compressor based multiplier.